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1CY M17 30
CYM1730
64K x 24 Static RAM Module
Features
* High-density 1.5M SRAM module * High-speed CMOS SRAMs -- Access time of 25 ns * 56-pin, 0.5-inch-high ZIP package * Low active power -- 2.8W (max. for tAA = 25 ns) * SMD technology * TTL-compatible inputs and outputs * Commercial temperature range * Small PCB footprint -- 1.05 sq. in. using six 32K x 8 static RAMs in SOJ packages mounted onto an epoxy laminate board with pins. Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the input/output pins (I/O0 through I/O23) of the device is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the chip select (CS) and output enable (OE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the input/output pins. The input/output pins remain in a high-impedance state unless the module is selected, outputs are enabled, and write enable is HIGH.
Functional Description
The CYM1730 is a high-performance 1.5M static RAM module organized as 64K words by 24 bits. This module is constructed
Logic Block Diagram
A0 - A14 OE WE 15
Pin Configuration
ZIP Top View
VCC I/O1 I/O3 I/O5 I/O7 GND A1 A3 A5 A7 NC GND I/O9 I/O11 I/O13 I/O15 NC OE A9 A11 A13 A15 GND I/O17 I/O19 I/O21 I/O23 VCC
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55
32K x 8 SRAM
32K x 8 SRAM
A15 CS
1 OF 2 DECODER 32K x 8 SRAM 32K x 8 SRAM
8
I/O16 - I/O23
8 32K x 8 SRAM 32K x 8 SRAM
I/O8 - I/O15
VCC I/O0 I/O2 I/O4 I/O6 GND A0 A2 A4 A6 CS NC I/O8 I/O10 I/O12 I/O14 GND WE A8 A10 A12 A14 GND I/O16 I/O18 I/O20 I/O22 VCC
1730-2
8
I/O0 - I/O7
1730-1
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 July 1991 - Revised January 1995
CYM1730
Selection Guide
1730-25 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 25 510 180 1730-30 30 510 180 1730-35 35 510 180
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -55C to +125C Ambient Temperature with Power Applied............................................... -10C to +85C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage ........................................... -0.5V to +7.0V
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 5V 10%
Electrical Characteristics Over the Operating Range
Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CS Power-Down Current[1] Automatic CS Power-Down Current[1] GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, CS < VIL Max. VCC, CS > VIH, Min. Duty Cycle = 100% Max. VCC, CS > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -20 -10 Min. 2.4 0.4 VCC + 0.3 0.8 +20 +10 510 180 180 Max. Unit V V V V A A mA mA mA
Capacitance[2]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 50 20 Unit pF pF
Notes: 1. A pull-up resistor to V CC on the CS input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 2. Tested on a sample basis.
2
CYM1730
AC Test Loads and Waveforms
481 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE 255 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 255 GND < 5 ns 481 3.0V 90% 10% 90% 10% < 5 ns ALL INPUT PULSES
(a)
1730-5
(b)
1730-3
1730-4
Equivalent to: OUTPUT
THEVENIN EQUIVALENT 167 1.73V
Switching Characteristics Over the Operating Range[3]
1730-25 Parameter READ CYCLE tRC tAA tOHA tACS tDOE tLZOE tHZOE tLZCS tHZCS WRITE tWC tSCS tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Output Hold from Address Change CS LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CS LOW to Low CYCLE[6] Write Cycle Time CS LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z[5] 25 20 22 2 2 20 13 2 3 0 10 30 25 25 2 2 23 15 2 3 0 10 35 30 30 2 2 25 20 2 5 0 15 ns ns ns ns ns ns ns ns ns ns Z[4] 5 10 CS HIGH to High Z[4, 5] 3 10 5 15 5 25 12 3 15 5 15 25 25 5 30 15 3 20 30 30 5 35 20 35 35 ns ns ns ns ns ns ns ns ns Description Min. Max. 1730-30 Min. Max. 1730-35 Min. Max. Unit
Notes: 3. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/I OH and 30-pF load capacitance. 4. At any given temperature and voltage condition, tHZCS is less than tLZCS for any given device. 5. tHZOE , tHZCS , and tLZCEare specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage. 6. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3
CYM1730
Switching Waveforms
Read Cycle No. 1 [7, 8]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1730-6
Read Cycle No. 2 [7, 9]
tRC CS tACS OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCS tPU VCC SUPPLY CURRENT 50% DATA VALID tPD ICC 50% ISB
1730-7
tHZOE tHZCS HIGH IMPEDANCE
Write Cycle No. 1 (WE Controlled) [6, 10]
tWC ADDRESS tSCS CS tAW tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED
1730-8
tHA tPWE
tHD
tLZWE HIGH IMPEDANCE
Notes: 7. WE is HIGH for read cycle. 8. Device is continuously selected, CS = VIL and OE= VIL. 9. Address valid prior to or coincident with CS transition LOW. 10. Data I/O will be high impedance if OE = VIH.
4
CYM1730
Switching Waveforms (continued)
Write Cycle No. 2 (CS Controlled) [6, 10, 11]
tWC ADDRESS tSA CS tAW tPWE WE tSD DATA IN DATA VALID tHZWE DATA OUT HIGH IMPEDANCE DATA UNDEFINED
1730-9
tSCS
tHA
tHD
Note: 11. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
CS H L L L WE X H L H OE X L X H Input/Outputs High Z Data Out Data In High Z Mode Deselect/Power-Down Read Word Write Word Deselect
Ordering Information
Speed (ns) 25 30 35 Ordering Code CYM1730PZ-25C CYM1730PZ-30C CYM1730PZ-35C Package Name PZ07 PZ07 PZ07 Package Type 56-Pin ZIP Module 56-Pin ZIP Module 56-Pin ZIP Module Operating Range Commercial Commercial Commercial
Document #: 38-M-00049-A
5
CYM1730
Package Diagram
56-Pin ZIP Module PZ07
2.990/3.010 .350 MAX.
.485/.495
.125/.175
2.750 REF
.100 REF
(c) Cypress Semiconductor Corporation, 1995. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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